This relates to electronic packages that contain an integrated circuit (IC) typically fabricated on a semiconductor die. The package protects the IC from the environment and provides I/O interfaces for the IC to communicate with other circuits.
FIG. 1 is a cross-sectional view of a prior art BGA package including a BGA substrate 100 and a semiconductor die 120 on the surface of the substrate 100. The semiconductor die carries an electronic circuit, e.g., a programmable logic device (PLD). The substrate includes a multitude of conductive paths running from an array of solder bumps 130 on one side of the substrate to an array of solder balls 160 on the other side of the substrate. The array of solder bumps 130 is located between the semiconductor die 120 and the substrate 100. After reflowing in a high temperature environment, e.g., 220° C., this array of solder bumps 130 forms an array of solder joints that connects the electronic circuit's I/O structures from the semiconductor die 120 to the substrate 100. An underfill layer 140 is injected into the space between the die 120 and the substrate 100 to reduce stress concentration at the solder joints and prevent electrical open failures caused by any disconnected solder joint. A heat spreader 180 may be positioned on top of the semiconductor die 120 and the substrate 100 to dissipate the heat generated by the package. A layer 150 of thermal interface material may be deployed between the die 120 and the heat spreader 180 to improve the package's heat transfer efficiency. The array of solder balls 160 is attached to an array of bonding pads 170 on the bottom side of the substrate 100, each solder ball being connected to one or more solder joints on the top side of the substrate 100 by one of the conductive paths in substrate 100. In a typical application, multiple BGA packages like the one shown in FIG. 1 are attached to a printed wiring board 190 by reflowing the solder balls 160 in a high temperature environment.
Copper traces in a BGA substrate are used as conductive paths, and each conductive path typically ends at a copper pad on each of the two sides of the substrate. To prevent a copper pad from being oxidized, its surface is often covered with a pad surface finish. A high-quality pad surface finish, in addition to insulating the copper pad from oxidization, is also expected to form a solid physical bond between the attached solder ball and the copper pad that is able to survive in extreme environments. The electroless Ni and immersion gold (ENIG) finish, one of the most popular pad surface finishes used in the industry, has been proven to be quite vulnerable when it is subject to shock impacts that occur frequently during shipment. In contrast, the solder-on-pad (SOP) finish significantly outperforms the ENIG finish in terms of shock resistance. Unfortunately, the SOP finish often behaves poorly during the board-level reliability (BLR) test, which is another critical factor when choosing an appropriate pad surface finish for a copper pad.
FIG. 2A is an enlarged cross-sectional view of a prior art bonding pad structure 200 at the bottom side of a substrate 205 before a solder ball is attached to its surface. The structure includes a copper pad 210 that is covered with a layer of solder mask 240 on its peripheral edge. The solder mask originally covering the central region of the copper pad 210 has been removed and the exposed pad surface is covered with a SOP finish 230 to protect it from oxidization. The SOP finish 230 is typically made of eutectic solder (63% Sn-37% Pb). As a result, a Cu/Sn intermetallic layer 235 is formed between the copper pad 210 and the SOP finish 230. Generally, the thickness of the Cu/Sn intermetallic layer is not uniform and its average is about 1–2 microns before solder reflow, i.e., a solder ball is attached to the bonding pad. However, the average thickness of the Cu/Sn intermetallic layer may grow to about 2.5–3.5 microns after multiple solder reflows. Mechanically, the Cu/Sn intermetallic layer is very brittle and it may easily break apart when subject to frequent thermal cycles.
FIG. 2B schematically illustrates the structure of FIG. 2A with a solder ball 250 attached to the copper pad 210 through solder reflow. A comparison of the bonding pad structure 200 before and after the solder reflow indicates that the Cu/Sn intermetallic layer 235 has become thicker since more tin in the SOP finish 230 has been absorbed into the layer 235. As a result, when a BGA package including the bonding pad structure 200 is subjected to a BLR thermal cycle test, a crack 237 may develop in the Cu/Sn intermetallic layer 235 that disconnects the solder ball 250 from the copper pad 210, causing an electrical open failure to the package.